--
-- CSSE2000 8 Bit Microprocessor
-- Copyright (C) 2011 Nathan Rossi (University of Queensland)
--
-- THIS DESIGN/CODE IS PROVIDED TO YOU UNDER THE FOLLOWING LICENSE:
--
-- All material is restricted to use in the CSSE2000 Project for 2011.
-- You may not redistribute the file/code/design, without the consent of the author.
--
-- DO NOT MODIFY THIS FILE
--

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library work;
use work.proc_package.ALL;

entity proc_sreg is
	port (
		rst : in std_logic;
		clk : in std_logic;
		en : in std_logic;
		
		input : in PROC_REG_DATA_TYPE;
		output : out PROC_REG_DATA_TYPE
	);
end proc_sreg;

architecture Behavioral of proc_sreg is
	-- Signal of stored value
	signal value : PROC_REG_DATA_TYPE := (others => '0');
begin

	-- Synchronous Register (with Async Reset)
	process (clk, rst)
	begin
		if rising_edge(clk) then
			if (rst = '1') then
				-- Reset to 0x00
				value <= (others => '0');
			elsif (en = '1') then
				-- Write the input only when enabled
				value <= input;
			end if;
		end if;
	end process;

	-- Output the value
	output <= value;

end Behavioral;

